// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  scd_reg_offset_field.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:42 Create file
// ******************************************************************************

#ifndef __SCD_REG_OFFSET_FIELD_H__
#define __SCD_REG_OFFSET_FIELD_H__

#define SCD_SCD_TOP_START_LEN    1
#define SCD_SCD_TOP_START_OFFSET 0

#define SCD_LIST_BASE_ADDR_LEN    32
#define SCD_LIST_BASE_ADDR_OFFSET 0

#define SCD_UP_BASE_ADDRESS_LEN    32
#define SCD_UP_BASE_ADDRESS_OFFSET 0

#define SCD_UP_LENGTH_LEN    32
#define SCD_UP_LENGTH_OFFSET 0

#define SCD_BUFFER_FIRST_ADDR_LEN    32
#define SCD_BUFFER_FIRST_ADDR_OFFSET 0

#define SCD_BUFFER_LAST_ADDR_LEN    32
#define SCD_BUFFER_LAST_ADDR_OFFSET 0

#define SCD_BUFFER_INI_ADDR_LEN    32
#define SCD_BUFFER_INI_ADDR_OFFSET 0

#define SCD_SCD_RESERVE_LEN      31
#define SCD_SCD_RESERVE_OFFSET   1
#define SCD_SCD_INTR_MASK_LEN    1
#define SCD_SCD_INTR_MASK_OFFSET 0

#define SCD_SCD_BYPASS_FLAG_LEN     1
#define SCD_SCD_BYPASS_FLAG_OFFSET  15
#define SCD_CFG_METADATA_EN_LEN     1
#define SCD_CFG_METADATA_EN_OFFSET  14
#define SCD_RDBUF_MMU_EN_LEN        1
#define SCD_RDBUF_MMU_EN_OFFSET     13
#define SCD_SCD_EMA_LEN             3
#define SCD_SCD_EMA_OFFSET          10
#define SCD_OTHER_MMU_EN_LEN        1
#define SCD_OTHER_MMU_EN_OFFSET     9
#define SCD_SCD_LOWDLY_EN_LEN       1
#define SCD_SCD_LOWDLY_EN_OFFSET    8
#define SCD_SCD_SAFE_MODE_LEN       1
#define SCD_SCD_SAFE_MODE_OFFSET    7
#define SCD_PES_CHECK_FLAG_LEN      1
#define SCD_PES_CHECK_FLAG_OFFSET   6
#define SCD_MPEG4_FPGA_FLAG_LEN     1
#define SCD_MPEG4_FPGA_FLAG_OFFSET  5
#define SCD_SLICE_CHECK_FLAG_LEN    1
#define SCD_SLICE_CHECK_FLAG_OFFSET 4
#define SCD_SCD_PROTOCOL_LEN        4
#define SCD_SCD_PROTOCOL_OFFSET     0

#define SCD_SCD_INT_FLAG_LEN    32
#define SCD_SCD_INT_FLAG_OFFSET 0

#define SCD_SCD_PREVIOUS_BYTE_LSB_LEN    32
#define SCD_SCD_PREVIOUS_BYTE_LSB_OFFSET 0

#define SCD_SCD_RST_BUSY_LEN    1
#define SCD_SCD_RST_BUSY_OFFSET 1
#define SCD_SCD_INT_FLAG_LEN    1
#define SCD_SCD_INT_FLAG_OFFSET 0

#define SCD_SCD_PREVIOUS_BYTE_MSB_LEN    16
#define SCD_SCD_PREVIOUS_BYTE_MSB_OFFSET 0

#define SCD_SCD_BYTES_VALID_LEN    6
#define SCD_SCD_BYTES_VALID_OFFSET 0

#define SCD_SHORT_HEADER_NUM_LEN    10
#define SCD_SHORT_HEADER_NUM_OFFSET 22
#define SCD_SCD_NUM_OUT_LEN         22
#define SCD_SCD_NUM_OUT_OFFSET      0

#define SCD_ROLL_ADDR_LEN    32
#define SCD_ROLL_ADDR_OFFSET 0

#define SCD_SCR_EATEN[30:0]_LEN    31
#define SCD_SCR_EATEN[30:0]_OFFSET 0

#define SCD_SEG_BUFFER_OFFSET_LEN    32
#define SCD_SEG_BUFFER_OFFSET_OFFSET 0

#define SCD_SEG_NEXT_ADDR_LEN    32
#define SCD_SEG_NEXT_ADDR_OFFSET 0

#define SCD_CUR_STA_WDAT_LEN    4
#define SCD_CUR_STA_WDAT_OFFSET 20
#define SCD_CUR_STA_RDAT_LEN    4
#define SCD_CUR_STA_RDAT_OFFSET 16
#define SCD_CUR_STA_DET_LEN     4
#define SCD_CUR_STA_DET_OFFSET  8
#define SCD_CUR_STA_MAIN_LEN    7
#define SCD_CUR_STA_MAIN_OFFSET 0

#define SCD_SDWR_NUM_BURST_LEN     5
#define SCD_SDWR_NUM_BURST_OFFSET  8
#define SCD_SDWR_CNT_BURST_LEN     4
#define SCD_SDWR_CNT_BURST_OFFSET  4
#define SCD_SDWR_CURR_STATE_LEN    3
#define SCD_SDWR_CURR_STATE_OFFSET 0

#define SCD_SCD_RUN_CYCLE_LEN    32
#define SCD_SCD_RUN_CYCLE_OFFSET 0

#define SCD_RD_REQ_NUM_LEN    32
#define SCD_RD_REQ_NUM_OFFSET 0

#define SCD_RD_DAT_NUM_LEN    32
#define SCD_RD_DAT_NUM_OFFSET 0

#define SCD_WR_REQ_NUM_LEN    32
#define SCD_WR_REQ_NUM_OFFSET 0

#define SCD_WR_DAT_NUM_LEN    32
#define SCD_WR_DAT_NUM_OFFSET 0

#define SCD_CUR_SCD_ST_LEN    32
#define SCD_CUR_SCD_ST_OFFSET 0

#define SCD_CLK_CFG[1:0]_LEN    2
#define SCD_CLK_CFG[1:0]_OFFSET 0

#define SCD_SCD_ARBIT_DG0_LEN    32
#define SCD_SCD_ARBIT_DG0_OFFSET 0

#define SCD_SCD_ARBIT_DG1_LEN    32
#define SCD_SCD_ARBIT_DG1_OFFSET 0

#define SCD_RCMD_C2A_FIFO_DG_LEN    32
#define SCD_RCMD_C2A_FIFO_DG_OFFSET 0

#define SCD_WCMD_C2A_FIFO_DG_LEN    32
#define SCD_WCMD_C2A_FIFO_DG_OFFSET 0

#define SCD_SOFTRST_STATE0_LEN    32
#define SCD_SOFTRST_STATE0_OFFSET 0

#define SCD_SOFTRST_STATE1_LEN    32
#define SCD_SOFTRST_STATE1_OFFSET 0

#define SCD_SCD_SAFE_INTR_MASK_LEN    1
#define SCD_SCD_SAFE_INTR_MASK_OFFSET 0

#define SCD_SCD_SAFE_INT_FLAG_LEN    1
#define SCD_SCD_SAFE_INT_FLAG_OFFSET 0

#endif // __SCD_REG_OFFSET_FIELD_H__
